A conventional voltage controlled oscillation circuit 100 shown in FIG. 10 comprises a quartz resonator X connected to between two terminals n1 and n2, a capacitor C1 and a varicap (voltage variable capacitance diode) VC1 serially connected to between the terminal n1 and ground GND, a capacitor C2 and a varicap VC2 serially connected to between the terminal n2 and the ground GND, resistance elements R1 and R2 serially connected to between a connection point of the capacitor C1 and the varicap VC1 and a connection point of the capacitor C2 and the varicap VC2, and a control input terminal n3 connected to a connection point of the resistance elements R1 and R2. A voltage level Vc of a control signal is applied to the control input terminals n3. Further provided are resistance elements R3 and R4 serially connected to between the terminals n1 and n2, an inverter In1 whose input side is connected to the terminal n1 and output side is connected to a connection point of the resistance elements R3 and R4, inverters In2 and In3 serially connected to the output side of the inverter In1, and an output terminal n4 connected to an output side of the inverter In3.
When power is supplied to the voltage controlled oscillation circuit 100, the voltage level Vc of the control signal is applied to the control input terminal n3. The voltage level Vc is applied to the varicaps VC1 and VC2 via the resistance elements R1 and R2. Then, capacitance values of the varicaps VC1 and VC2 change in response to the voltage level Vc, and an oscillation frequency due to resonance specific to the quartz resonator X accordingly changes within a predetermined range. Thus, a signal of the oscillation frequency in response to the voltage level Vc of the control signal is outputted from the inverter In1 to be waveform-shaped and amplified via the inverters In2 and In3 and then it is outputted outside from the output terminal n4.
In the voltage controlled oscillation circuit 100, when the voltage level Vc of the control signal applied to the control input terminal n3 is relatively small, the capacitance values of the varicaps VC1 and VC2 are relatively large. As a result, a long time is required to start the oscillation.
In contrast to the foregoing constitution, a method was proposed, wherein a start voltage is given to be able to stabilize the oscillation better than the voltage level of the control signal in the normal oscillation at supplying the power, and the voltage is switched to normal control through a voltage control terminal after the oscillation is stabilized, (for example, see No. 2002-237722 of the Publication of the Unexamined Japanese Patent Applications (see Page 2-3 and FIG. 1)).
Describing the foregoing constitution, an applied voltage control circuit 70 for the voltage controlled oscillation circuit is constructed as shown in FIG. 11. When the power supply is turned on, an oscillation start-up recognizing circuit 71 outputs “L” level as a control signal ST until the oscillation of the voltage controlled oscillation circuit 100 is detected. At the time, an NMOS transistor and a PMOS transistor of a transmission gate G3 are in a disconnected state, and the transmission gate G3 is also in the disconnected state. Because the control signal ST is at the “L” level, a PMOS transistor P4 is conducted, and a power-supply voltage VDD is applied to the control input terminal n3 of the voltage controlled oscillation circuit 100. Since the power-supply voltage VDD is sufficiently higher than the voltage level Vc of the control signal, the time required for starting the oscillation of the quartz resonator X is reduced. Then, the oscillation start-up recognizing circuit 71 detects that the oscillation of the voltage controlled oscillation circuit 100 has been stabilized, and inverts the control signal ST to “H” level. As a result, the PMOS transistor P4 is disconnected, and the transmission gate G3 is now conducted. Then, the voltage level Vc of the control signal from the voltage control terminal 72 is applied to the control input terminal n3 via the transmission gate G3. Thus, the control operation shifts to the conventional control state.
As an integration of LSI becomes higher reductions of power consumption of the LSI itself and an internal power-supply voltage are done, and it is predicted that a level of a power-supply voltage for a digital terminal is also reduced. As a first problem, there causes a possibility that “H” level of a general purpose port, which can be controlled by the LSI or external microcomputer, may not satisfy a minimum allowable value to recognize the “H” level of the transmission gate. As a result, the transmission gate cannot be conducted after the oscillation is stabilized, which makes the control through the voltage control terminal impossible.
As a second problem, when gates of the PMOS transistor and the transmission gate are switched immediately after the power supply is turned on and after the oscillation is stabilized, a period when the PMOS transistor and the transmission gate are simultaneously conducted is generated due to influences such as a delay of the inverter resulting from the inversion of the signal. As a result, the power-supply voltage is applied to the voltage control terminal, which is likely to cause an overload to a control port of the LSI or external microcomputer.